SOC Yield & Diagnostics Engineer, AI Hardware

About This Role

Own and develop volume diagnostic flows for ATPG/BIST, analyze volume data, and drive corrective actions with foundries to accelerate yield ramp for AI hardware.

Responsibilities

• Architect and set up volume diagnostic data processing pipelines for SOC logic and memory
• Partner with EDA vendors, integrate AI-based deep learning techniques to improve diagnostics convergence, fault isolation, and failure analysis success
• Collaborate with foundry partners to accelerate defect reduction – build defect Paretos, recommend FA candidates, validate improvements from process changes
• Develop models to predict yield trends, detect anomalies, prefetch corrective actions
• Work with DFT and PTE teams to root cause qualification fails/field returns, aid development of new tests targeting specific fault types

Requirements

• 5+ years of experience in ATPG and SRAM BIST diagnostics, fault isolation, failure analysis
• Solid understanding in CMOS fabrication process in latest FinFET/GAA technologies
• Good understanding of DFT implementation of ATPG and MBIST
• Experience using industry standard EDA diagnostics offerings from Tessent/Synopsys

Qualifications

• Degree in Electrical Engineering, Computer Science or related fields, or equivalent experience
• 5+ years of experience in ATPG and SRAM BIST diagnostics, fault isolation, failure analysis

Nice to Have

• Strong automation skills
• Building python based AI data analysis routines

Skills

* Required skills

Benefits