Physical Design Engineer, ASIC

About This Role

As a Physical Design Engineer, you will contribute to the physical design of blocks and the full chip from RTL-to-GDS, collaborating with internal and external teams to optimize power/performance analysis (PPA). This role is critical in driving cutting-edge TPU technology for Google's AI/ML applications.

Responsibilities

• Participate in the physical design of blocks
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS
• Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA)
• Conduct feasibility studies for new microarchitectures and optimizing runs for finished RTL
• Collaborate with RTL, design for testing (DFT), floorplan, and full-chip Signoff teams
• Solve technical problems with micro-architecture and practical logic circuits solutions
• Evaluate design options with optimized performance, power, and area in mind

Requirements

• 2 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floor planning, place and route, and timing closure)
• Experience in Python, Tcl, or Perl scripting

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floor planning, place and route, and timing closure)

Nice to Have

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
• Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.)
• Experience working with external partners on physical design (PD) closure
• Experience in static timing analysis (STA), with an understanding of how to define timing corners, margins and derates
• Understanding of DFT including Scan, MBIST and LBIST
• Understanding of performance, power and area (PPA) trade-offs

Skills

* Required skills

Benefits