ASIC Design Verification Engineer, Machine Learning, Google Cloud

About This Role

This role will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology, developing custom silicon solutions for Google's AI/ML applications. The engineer will contribute to the innovation behind products loved by millions worldwide, leveraging design and verification expertise to verify complex digital designs. The focus will be on TPU architecture and its integration within AI/ML-driven systems.

Responsibilities

• Plan the verification of complex design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and universal verification methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with SystemVerilog (e.g., SystemVerilog Assertions or functional coverage).

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Nice to Have

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 2 years of experience with the full verification life cycle.
• Experience with Universal Verification Methodology (UVM).
• Experience verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience in power aware verification, gate level simulations, and post silicon bring-up.

Skills

* Required skills

Benefits