Virtual Platform Engineer

About This Role

This role will shape next-generation AR/VR systems by developing high-fidelity virtual platforms for early software enablement and silicon innovation. You will model advanced SoC architecture, collaborate with architects and designers, and validate custom hardware to accelerate delivery of high-performance silicon.

Responsibilities

• Build SystemC/TLM models representing SoC components including processors, DSPs, NoCs, DMA engines, memory controllers, and custom accelerators
• Integrate internal and vendor IP into cohesive Virtual Platforms with automated workflows that ensure complete connectivity, register accuracy, and CI enablement
• Collaborate with architects, designers, and verification teams to deliver fast, cycle‑approximate C++ models for first‑party IP
• Support hardware programs by validating evolving SoC architectures with system software and firmware teams
• Enhance virtual platforms with instrumentation for power, performance, and architectural trade‑off analysis

Requirements

• 7+ years of industry experience, including 5+ years in hardware modeling, virtual platforms, or SoC performance modeling
• Expertise in modern C++ for chip‑design, EDA, simulation, and C++ concurrency (threads, atomics, memory ordering)
• Hands‑on experience with SystemC/TLM and virtual platform tools such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
• Strong understanding of processor/DSP architectures (ARM, RISC‑V, Xtensa), NoC/MMU/cache systems
• Proficiency in Python for automation

Qualifications

• Bachelor’s degree in computer science, Electrical Engineering, or equivalent experience
• 7+ years of industry experience, including 5+ years in hardware modeling, virtual platforms, or SoC performance modeling

Skills

* Required skills

Benefits