Senior ASIC Physical Design Engineer

About This Role

Join the Cisco Acacia Communications team as a Senior Physical Design Engineer, developing intelligent transceivers for fiber optic transmission. You will drive RTL-to-GDSII implementation, optimize design flows, and collaborate to deliver high-performance networking chips.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm)
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools
• Implement and manage timing ECO strategies
• Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues related to design, tools, etc.
• Evaluate and implement new timing methodologies; provide creative debugging solutions
• Contribute to best practices and drive methodology alignment across projects

Requirements

• 7+ years of related experience with a Bachelor's degree, or 4+ years of related experience with a Master's degree in Computer or Electrical Engineering
• Hands-on experience in ASIC physical design and implementation
• Experience with place & route using tools such as Cadence Innovus, Synopsys ICC2, or industry equivalent tools
• Experience with industry standard CAD methodologies (Cadence, Synopsys, or Mentor)

Qualifications

• Bachelors degree in Computer or Electrical Engineering or Masters degree in Computer or Electrical Engineering
• 7+ years of related experience with a Bachelor's degree, or 4+ years with a Master's degree in ASIC physical design and implementation

Nice to Have

• Experience with floor planning & partitioning, formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR
• Experience with Static Timing Analysis including tools such as PrimeTime-DMSA or Tempus
• Experience with Scripting using languages such as TCL, Perl, Python, etc.
• Synthesis experience including Synopsys DC/FC
• Formal Verification experience using tools such Synopsys Formality or Cadence LEC
• Experience with Power Integrity including tools such as Apache Redhawk or Voltus
• Physical Verification DRC/LVS experience including tools such as Synopsys ICV or Mentor Calibre

Skills

* Required skills

Benefits