Principal Engineer - Design Implementation

About This Role

As a Principal Engineer in Design Implementation within the MCU IC Design-HP group, you will be responsible for the synthesis, static timing analysis (STA), and timing closure of 32-bit controllers, driving power optimization and logic verification using an industry-leading ASIC design flow.

Responsibilities

• Responsible for Design Implementation (Synthesis/STA/Timing closure) of 32-bit controllers
• Drive and optimize synthesis, power optimization, static timing analysis, and logic verification using an industry leading ASIC design flow
• Drive and enhance Synthesis, Static Timing and Power Optimization methodologies for the MCU32 silicon design group
• Develop timing constraints, drive SoC timing budgets, power optimization, formal verification, timing closure and other sign-off activities
• Drive low power implementation and optimization methodologies using UPF/CPF
• Work closely with digital, analog, and physical design teams to optimize for performance, power, and area

Requirements

• Extensive experience in RTL2Netlist implementation flows
• Strong knowledge in Cadence & Synopsys tools for synthesis, static timing analysis and other activities
• Strong scripting skills in TCL, Perl and other programming languages
• Synthesis and timing closure ownership for 32-bit Microcontroller designs
• Very good inter personal skills and able to interact well with other members in the functional teams of the business unit
• Good communication skills

Qualifications

• Bachelor’s degree in electrical engineering
• At least 10+ years of experience in ASIC implementation activities such as synthesis and STA

Skills

* Required skills

Benefits