Senior Validation Engineering Manager

OSI Engineering San Jose, CA $136,000 - $252,600
Full Time Manager Level 5+ years

Posted 2 months ago Expired

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About This Role

Lead and manage a team of validation engineers for a leading chip and silicon IP provider, focusing on bench validation and electrical characterization of high-performance memory buffer chips. This role involves both hands-on technical work and leadership responsibilities, contributing to products that enhance data speed and security.

Responsibilities

  • Lead and directly contribute to hands-on bench validation and electrical characterization activities (20–30% of time)
  • Manage and mentor a small team of 2–5 validation engineers, ensuring technical excellence and project alignment
  • Partner with Design, Architecture, Verification, and Operations teams to deliver top-quality buffer chip products
  • Develop and continuously refine validation methodologies, improving design coverage, efficiency, and time-to-market
  • Collaborate with internal and external partners for test equipment sourcing, PCB fabrication, and assembly
  • Develop automation frameworks and Python-based validation scripts for data collection and analysis
  • Define and execute test methodologies to validate silicon designs against specifications
  • Contribute to project planning, budgeting, and resource allocation

Requirements

  • 5+ years of hands-on bench validation experience in semiconductor or system-level environments
  • Proven experience with DDR4/DDR5 memory interfaces and processor/memory system architectures
  • Demonstrated proficiency in Python scripting for validation, automation, and data analysis
  • Strong understanding of electrical characterization, signal integrity, and power integrity
  • Experience managing small teams or leading technical projects as an individual contributor with leadership responsibilities

Qualifications

  • B.S. or M.S. in Electrical Engineering or related field
  • 5+ years of hands-on bench validation experience in semiconductor or system-level environments

Nice to Have

  • Background in SerDes or PCIe PHY characterization
  • Experience with ATE or system-level testing

Skills

Python * PCIe * SERDES * DDR4 * DDR5 * PCIe PHY * Signal Integrity * Power Integrity *

* Required skills

Benefits

Vision plan
RSUs
Dental plan
Medical plan

About OSI Engineering

A leading chip and silicon IP provider.

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