Senior Principal Engineer, IP Design (ASIC)

About This Role

This role involves leading the end-to-end design and verification of complex IP blocks for high-performance memory controllers at SK hynix memory solutions America. The Senior Principal Engineer will drive methodology improvements and mentor staff engineers to achieve first-pass silicon success for next-generation enterprise and AI data center storage solutions.

Responsibilities

• Architect, design, and verify complex IP blocks or subsystems for high-performance memory controllers from specification to tapeout.
• Develop efficient, high-speed RTL (Verilog/SystemVerilog) for critical modules, optimizing for power, performance, and area (PPA).
• Oversee design reviews, linting, Clock Domain Crossing (CDC) analysis, and power analysis for robust functional and timing closure.
• Collaborate with verification, DFT, physical design, and firmware teams to resolve complex system-level bottlenecks.
• Drive enhancements in design automation (Python/Tcl/Perl) and best practices for synthesis and static timing analysis (STA).
• Mentor junior and staff engineers on advanced design techniques, code quality, and debugging strategies.

Requirements

• 12+ years of hands-on experience in ASIC/SoC design with successful tapeouts
• Expert proficiency in Verilog/SystemVerilog, logic design, synthesis, and STA for high-speed digital circuits
• Strong experience with industry-standard EDA tools (Synopsys/Cadence) for simulation, linting, and CDC analysis
• Demonstrated ability to lead technical discussions and document complex micro-architectures

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of hands-on experience in ASIC/SoC design with a proven track record of successful tapeouts.

Nice to Have

• Master’s or PhD in Electrical Engineering with 8+ years of applicable experience
• Deep understanding of memory controller architectures (PCIe/NVMe, DDR, NAND Flash) or error correction algorithms
• Experience designing for high-frequency interfaces or data center/enterprise applications
• Proficiency in Python, Tcl, or Perl for design automation and flow optimization
• Previous experience serving as a technical lead or architect for a major subsystem or IP block

Skills

* Required skills

Benefits