Senior DFT Engineer

About This Role

Implement and validate Design for Test (DFT) logic for SoC and sub-system levels, collaborating with cross-functional teams from early investigation through tape-out and silicon testing.

Responsibilities

• Implement DFT logic into SoC and sub-system level and validate all DFT features using industry standard simulation tools
• Verify DFT logic in RTL and gate level simulations
• Generate ATPG patterns and debug coverage issues to meet target
• Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure
• Participate in ATE targeted test patterns generation, validation and silicon- debug activities
• Collaborate with Test and product engineering teams on silicon characterization and validation

Requirements

• 7+ years of experience in Design for Test (DFT)
• Core DFT skills including Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
• Experience coding Verilog RTL, TCL and/or Perl

Qualifications

• 7+ years of proven experience in Design for Test

Nice to Have

• Familiarity with SoC style architectures including multi-clock domain and low power design practices
• Familiarity with Arm IP like Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
• Background in high performance design, implementation and DFT timing constraints
• Experience in datacenter chips
• Experience with 2.5D and 3D test
• Ability to work both collaboratively on a team and independently
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task

Skills

* Required skills