RFIC Layout Engineer

About This Role

This role focuses on advancing RF analog circuit integration for wireless transceivers in advanced technology nodes. The engineer will address daily layout challenges, collaborate with RFIC design and layout teams, and continuously improve products to enhance user experiences.

Responsibilities

• Perform floorplanning, placement, routing, and verification for custom RF circuit blocks
• Verify and refine layouts through simulation to meet design requirements
• Diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre
• Identify challenges and propose solutions to streamline layout tasks
• Collaborate with teams to specify and finalize layout methodologies

Requirements

• 3+ years of industry experience
• Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond)
• Proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions
• Familiarity with sophisticated process effects such as LOD, WPE, and DFM
• Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up

Qualifications

• BS
• 3+ years of industry experience

Nice to Have

• Experience in sophisticated DRC, ERC, LVS verification, and debugging
• Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs
• RF experience

Skills

* Required skills

Benefits