Physical Design Technical Lead/Engineer

About This Role

Lead and execute physical design implementation tasks from netlist to GDSII for FPGA/SoC devices, ensuring performance, power, and area (PPA) goals are met. Collaborate with various design teams and optimize physical design flows with automation.

Responsibilities

• Lead and execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII
• Apply PPA optimization techniques (performance / timing closure, power reduction, area efficiency) across blocks or full-chip hierarchies
• Collaborate with front-end design, architecture, CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets and DFT Insertions are met
• Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR and reduce manual intervention
• Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign-off readiness
• Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization
• Work closely with manufacturing and packaging partners to ensure implementation is manufacturable (DFM/DFY), meets yield targets and meets high-volume production requirements
• Debug physical design issues, interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds
• Mentor and collaborate with junior engineers; contribute to reviews, documentation of flows, and continuous process improvement

Requirements

• 10+ years of experience in digital/SoC physical design (synthesis through P&R through sign‐off)
• Hands-on experience with industry‐standard EDA tools (e.g., Synopsys IC Compiler/ Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high speed digital ASIC/SoC implementation
• Scripting/programming experience (TCL, Python, Perl, shell) for flow automation and productivity enhancement
• Physical design flow experience: floor-planning, CTS, placement, routing, gating power domains, clock domain crossing, multi-power domain design, timing closure, ECOs, DRC/LVS/DFM issues
• Experience in power/IR analysis, signal/power integrity reports, and propose corrective actions
• Experience interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, manufacturing and packaging teams

Qualifications

• Bachelor’s in Electrical Engineering, Computer Engineering or related field
• 10+ years of experience in digital/SoC physical design (synthesis through P&R through sign‐off)

Nice to Have

• Hands-on experience with Primetime (Tempus)
• Hands-on experience with Fusion Compiler (ICC/ICC2/Innovus)
• Hands-on experience with Calibre
• Hands-on experience with Conformal (Formality)
• Hands-on experience with Redhawk (Voltus)
• Hands-on experience with Tetramax/Tessent

Skills

* Required skills