Application Specific Integrated Circuit Design Engineer
ACL Digital
Austin, TX
Contract
Mid Level
Posted 1 month ago Expired
This job has expired
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Upload Your ResumeAbout This Role
Design and develop Register Transfer Level (RTL) for System IP blocks using Verilog/SystemVerilog, collaborating with various engineering teams to support silicon bring-up, debug, timing, and coverage closure while developing and maintaining front-end tools and automation scripts.
Responsibilities
- Design and develop RTL for System IP blocks using Verilog/SystemVerilog
- Collaborate with verification, physical design, power, and performance teams
- Develop and maintain front-end tools, flows, and automation scripts
- Support silicon bring-up, debug, timing, and coverage closure
Requirements
- Strong RTL design experience with Verilog/SystemVerilog
- Hands-on experience with synthesis, LEC, lint, and low-power tools
Skills
SystemVerilog
*
Verilog
*
Synthesis
*
LEC
*
Lint
*
Low-power tools
*
* Required skills